The present invention relates to solid-state image sensors, specifically to CMOS image sensors that have very small pixel sizes. In particular this invention relates to pixels that use only two transistors (2T) and two diodes for the reset and addressing instead of the typical reset and addressing transistors. Furthermore the diodes can be built vertically on top of a silicon substrate and have a very small size in order not to occupy a valuable pixel area. The described pixels are still capable of standard low noise correlated double sampling operation as is typically used with 4T pixel architectures.
Typical image sensors sense light by converting impinging photons into electrons that are integrated (collected) in sensor pixels. After completion of integration cycle, collected charge is converted into a voltage, which is supplied to output terminals of the sensors. In typical CMOS image sensors, the charge to voltage conversion is accomplished directly in the pixels themselves and the analog pixel voltage is transferred to the output terminals through various pixel addressing and scanning schemes.
The analog signal can also be converted on-chip to a digital equivalent before reaching the chip output. The pixels have incorporated in them a buffer amplifier, typically a source follower, which drives the sense lines that are connected to the pixels by suitable addressing transistors. After charge to voltage conversion is completed and the resulting signal is transferred out from the pixels, the pixels are reset in order to be ready for accumulation of new charge. In pixels that are using Floating Diffusion (FD) as a charge detection node, the reset is accomplished by turning on a reset transistor that momentarily conductively connects the FD node to a voltage reference. This step removes collected charge; however, it generates kTC-reset noise as is well known in the art. The kTC noise has to be removed from the resulting signal by the Correlated Double Sampling (CDS) signal processing technique in order to achieve desired low noise performance. The typical CMOS sensors that utilize the CDS concept need to have four transistors (4T) in the pixel. An example of the 4T pixel circuit can be found in the U.S. Pat. No. 5,991,184 to Guidash.
Recently a new pixel operation technique is gaining popularity in the literature and in many products. A 3T pixel where the addressing transistor is eliminated from the pixel is introduced. In an image sensor with the 3T pixel, the pixel addressing is accomplished by a source follower transistor itself through applying a suitable bias on FD nodes that are not selected. The latest description of this concept can be found for example in the: ISSCC 2007 Digest of Technical Papers, “A 1/2.7 inch Low-Noise CMOS Image Sensor for Full HD Camcorders” pp. 510˜511, by Hidekazu Takahashi et al. Eliminating the addressing transistor from the pixel saves the valuable pixel area and also eliminates one control wire that was needed for controlling the addressing transistor gate.
FIG. 1 illustrates a simplified circuit diagram of a typical 3T CMOS image sensor pixel with a pinned photodiode for sensing light and switched drain bias for addressing.
Referring to FIG. 1, a photodiode 101 is coupled through a charge transfer transistor 102 to a FD node 103. A sensing source follower (SF) transistor 104 has its gate connected to the FD node 103, a drain connected to a Vdd node 105 and a source connected to an output column bus 106. The Vdd node 105 is connected to a Vdd column bus 107 and a drain switch 108. The FD node 103 is reset to the Vdd node 105 by a reset transistor 109. A gate of the reset transistor 109 is controlled by a row bus line 110 and the gate of the charge transfer transistor 102 is controlled by a second row bus line 111. As photons 112 impinge on the photodiode 101, electron charge is generated there. After completion of charge integration, the FD node 103 is reset and all charge from the photodiode 101 is transferred on the FD node 103. This changes a FD voltage from an original reset level to a new signal level. Both of the reset level and the signal level on the FD node 103 are then sensed by the transistor 104 and both levels are transferred onto the output bus 106 and further into column signal processing circuits for subtraction and additional processing. The subtraction of the reset level from the signal level is called Correlated Double Sampling (CDS), which removes the kTC noise and the transistor threshold non-uniformities from the signal. In order to prevent interference from signals that are generated on the transistors 104 of pixels in the remaining rows that are not addressed and are connected to the same column 106, the FD nodes of these transistors are set low. This turns the SF of these pixels off, since the SF of the selected pixel is biased high.
The advantages of the 3T pixel circuit are that fewer transistors occupy less pixel area and the elimination of the addressing transistor eliminates the gate addressing line, lowers the pixel output impedance, and thus eliminates noise generated in that transistor. However, the 3T still occupy a significant amount of the valuable active pixel area, which is a problem for further reduction of pixel size and thus cost of the CMOS image sensors. This disadvantage is often times compensated by sharing the pixel circuit with several photodiodes. However, the circuit sharing has also its disadvantages. In such circuits, the FD node capacitance is increased, which reduces the pixel sensitivity, and the interconnection lines also occupy the valuable pixel area. Other disadvantages of the sharing concept are slightly asymmetrical layout and electrical functions that result in some asymmetrical optical as well as electrical cross talk problems. It is therefore desirable to design pixel that have very small size and that do not require excessive sharing of the circuits.